\doxysection{stm32h7xx\+\_\+ll\+\_\+dma.\+h}
\hypertarget{stm32h7xx__ll__dma_8h_source}{}\label{stm32h7xx__ll__dma_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_dma.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_ll\_dma.h}}
\mbox{\hyperlink{stm32h7xx__ll__dma_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{00021\ \textcolor{preprocessor}{\#define\ STM32H7xx\_LL\_DMA\_H}}
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\DoxyCodeLine{00035\ \textcolor{preprocessor}{\#if\ defined\ (DMA1)\ ||\ defined\ (DMA2)}}
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\DoxyCodeLine{00047\ \textcolor{keyword}{static}\ \textcolor{keyword}{const}\ uint8\_t\ LL\_DMA\_STR\_OFFSET\_TAB[]\ =}
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\DoxyCodeLine{00049\ \ \ (uint8\_t)(DMA1\_Stream0\_BASE\ -\/\ DMA1\_BASE),}
\DoxyCodeLine{00050\ \ \ (uint8\_t)(DMA1\_Stream1\_BASE\ -\/\ DMA1\_BASE),}
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\DoxyCodeLine{00075\ \textcolor{preprocessor}{\#define\ LL\_DMA\_INSTANCE\_TO\_DMAMUX\_CHANNEL(\_\_DMA\_INSTANCE\_\_)\ \ \ \(\backslash\)}}
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\DoxyCodeLine{00189\ \}\ LL\_DMA\_InitTypeDef;}
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\DoxyCodeLine{00418\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream0))\ ?\ LL\_DMA\_STREAM\_0\ :\ \(\backslash\)}}
\DoxyCodeLine{00419\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream1))\ ?\ LL\_DMA\_STREAM\_1\ :\ \(\backslash\)}}
\DoxyCodeLine{00420\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream1))\ ?\ LL\_DMA\_STREAM\_1\ :\ \(\backslash\)}}
\DoxyCodeLine{00421\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream2))\ ?\ LL\_DMA\_STREAM\_2\ :\ \(\backslash\)}}
\DoxyCodeLine{00422\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream2))\ ?\ LL\_DMA\_STREAM\_2\ :\ \(\backslash\)}}
\DoxyCodeLine{00423\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream3))\ ?\ LL\_DMA\_STREAM\_3\ :\ \(\backslash\)}}
\DoxyCodeLine{00424\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream3))\ ?\ LL\_DMA\_STREAM\_3\ :\ \(\backslash\)}}
\DoxyCodeLine{00425\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream4))\ ?\ LL\_DMA\_STREAM\_4\ :\ \(\backslash\)}}
\DoxyCodeLine{00426\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream4))\ ?\ LL\_DMA\_STREAM\_4\ :\ \(\backslash\)}}
\DoxyCodeLine{00427\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream5))\ ?\ LL\_DMA\_STREAM\_5\ :\ \(\backslash\)}}
\DoxyCodeLine{00428\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream5))\ ?\ LL\_DMA\_STREAM\_5\ :\ \(\backslash\)}}
\DoxyCodeLine{00429\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1\_Stream6))\ ?\ LL\_DMA\_STREAM\_6\ :\ \(\backslash\)}}
\DoxyCodeLine{00430\ \textcolor{preprocessor}{\ ((uint32\_t)(\_\_STREAM\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2\_Stream6))\ ?\ LL\_DMA\_STREAM\_6\ :\ \(\backslash\)}}
\DoxyCodeLine{00431\ \textcolor{preprocessor}{\ LL\_DMA\_STREAM\_7)}}
\DoxyCodeLine{00432\ }
\DoxyCodeLine{00439\ \textcolor{preprocessor}{\#define\ \_\_LL\_DMA\_GET\_STREAM\_INSTANCE(\_\_DMA\_INSTANCE\_\_,\ \_\_STREAM\_\_)\ \ \ \(\backslash\)}}
\DoxyCodeLine{00440\ \textcolor{preprocessor}{((((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_0)))\ ?\ DMA1\_Stream0\ :\ \(\backslash\)}}
\DoxyCodeLine{00441\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_0)))\ ?\ DMA2\_Stream0\ :\ \(\backslash\)}}
\DoxyCodeLine{00442\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_1)))\ ?\ DMA1\_Stream1\ :\ \(\backslash\)}}
\DoxyCodeLine{00443\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_1)))\ ?\ DMA2\_Stream1\ :\ \(\backslash\)}}
\DoxyCodeLine{00444\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_2)))\ ?\ DMA1\_Stream2\ :\ \(\backslash\)}}
\DoxyCodeLine{00445\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_2)))\ ?\ DMA2\_Stream2\ :\ \(\backslash\)}}
\DoxyCodeLine{00446\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_3)))\ ?\ DMA1\_Stream3\ :\ \(\backslash\)}}
\DoxyCodeLine{00447\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_3)))\ ?\ DMA2\_Stream3\ :\ \(\backslash\)}}
\DoxyCodeLine{00448\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_4)))\ ?\ DMA1\_Stream4\ :\ \(\backslash\)}}
\DoxyCodeLine{00449\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_4)))\ ?\ DMA2\_Stream4\ :\ \(\backslash\)}}
\DoxyCodeLine{00450\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_5)))\ ?\ DMA1\_Stream5\ :\ \(\backslash\)}}
\DoxyCodeLine{00451\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_5)))\ ?\ DMA2\_Stream5\ :\ \(\backslash\)}}
\DoxyCodeLine{00452\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_6)))\ ?\ DMA1\_Stream6\ :\ \(\backslash\)}}
\DoxyCodeLine{00453\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA2))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_6)))\ ?\ DMA2\_Stream6\ :\ \(\backslash\)}}
\DoxyCodeLine{00454\ \textcolor{preprocessor}{\ (((uint32\_t)(\_\_DMA\_INSTANCE\_\_)\ ==\ ((uint32\_t)DMA1))\ \&\&\ ((uint32\_t)(\_\_STREAM\_\_)\ ==\ ((uint32\_t)LL\_DMA\_STREAM\_7)))\ ?\ DMA1\_Stream7\ :\ \(\backslash\)}}
\DoxyCodeLine{00455\ \textcolor{preprocessor}{\ DMA2\_Stream7)}}
\DoxyCodeLine{00456\ }
\DoxyCodeLine{00460\ }
\DoxyCodeLine{00464\ }
\DoxyCodeLine{00465\ }
\DoxyCodeLine{00466\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{00470\ }
\DoxyCodeLine{00489\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableStream(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00490\ \{}
\DoxyCodeLine{00491\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00492\ }
\DoxyCodeLine{00493\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaabf69fe92e9a44167535365b0fe4ea9e}{DMA\_SxCR\_EN}});}
\DoxyCodeLine{00494\ \}}
\DoxyCodeLine{00495\ }
\DoxyCodeLine{00511\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableStream(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00512\ \{}
\DoxyCodeLine{00513\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00514\ }
\DoxyCodeLine{00515\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaabf69fe92e9a44167535365b0fe4ea9e}{DMA\_SxCR\_EN}});}
\DoxyCodeLine{00516\ \}}
\DoxyCodeLine{00517\ }
\DoxyCodeLine{00533\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledStream(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00534\ \{}
\DoxyCodeLine{00535\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00536\ }
\DoxyCodeLine{00537\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaabf69fe92e9a44167535365b0fe4ea9e}{DMA\_SxCR\_EN}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaabf69fe92e9a44167535365b0fe4ea9e}{DMA\_SxCR\_EN}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{00538\ \}}
\DoxyCodeLine{00539\ }
\DoxyCodeLine{00574\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ConfigTransfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Configuration)}
\DoxyCodeLine{00575\ \{}
\DoxyCodeLine{00576\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00577\ }
\DoxyCodeLine{00578\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,}
\DoxyCodeLine{00579\ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga16bc78076551c42cbdc084e9d0006bd4}{DMA\_SxCR\_DIR}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc248dbc519cc580621cdadcdd8741fb}{DMA\_SxCR\_CIRC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga29c5d5c559dd14646fdc170e74f1f03b}{DMA\_SxCR\_PINC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga771a295832a584a3777ede523a691719}{DMA\_SxCR\_MINC}}\ |\ DMA\_SxCR\_PSIZE\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae9a98cb706a722d726d8ec6e9fe4a773}{DMA\_SxCR\_MSIZE}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga14c115d71a4e3b3c4da360108288154c}{DMA\_SxCR\_PL}}\ |\ \(\backslash\)}
\DoxyCodeLine{00580\ \ \ \ \ \ \ \ \ \ \ \ \ \ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11f412d256043bec3e01ceef7f2099f2}{DMA\_SxCR\_PFCTRL}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\_SxCR\_DBM}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd36c677ee53f56dc408cd549e64cf7d}{DMA\_SxCR\_CT}},\ Configuration);}
\DoxyCodeLine{00581\ \}}
\DoxyCodeLine{00582\ }
\DoxyCodeLine{00602\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetDataTransferDirection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ \ Direction)}
\DoxyCodeLine{00603\ \{}
\DoxyCodeLine{00604\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00605\ }
\DoxyCodeLine{00606\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga16bc78076551c42cbdc084e9d0006bd4}{DMA\_SxCR\_DIR}},\ Direction);}
\DoxyCodeLine{00607\ \}}
\DoxyCodeLine{00608\ }
\DoxyCodeLine{00627\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetDataTransferDirection(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00628\ \{}
\DoxyCodeLine{00629\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00630\ }
\DoxyCodeLine{00631\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga16bc78076551c42cbdc084e9d0006bd4}{DMA\_SxCR\_DIR}}));}
\DoxyCodeLine{00632\ \}}
\DoxyCodeLine{00633\ }
\DoxyCodeLine{00654\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Mode)}
\DoxyCodeLine{00655\ \{}
\DoxyCodeLine{00656\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00657\ }
\DoxyCodeLine{00658\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc248dbc519cc580621cdadcdd8741fb}{DMA\_SxCR\_CIRC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11f412d256043bec3e01ceef7f2099f2}{DMA\_SxCR\_PFCTRL}},\ Mode);}
\DoxyCodeLine{00659\ \}}
\DoxyCodeLine{00660\ }
\DoxyCodeLine{00680\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00681\ \{}
\DoxyCodeLine{00682\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00683\ }
\DoxyCodeLine{00684\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadc248dbc519cc580621cdadcdd8741fb}{DMA\_SxCR\_CIRC}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga11f412d256043bec3e01ceef7f2099f2}{DMA\_SxCR\_PFCTRL}}));}
\DoxyCodeLine{00685\ \}}
\DoxyCodeLine{00686\ }
\DoxyCodeLine{00705\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetPeriphIncMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ IncrementMode)}
\DoxyCodeLine{00706\ \{}
\DoxyCodeLine{00707\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00708\ }
\DoxyCodeLine{00709\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga29c5d5c559dd14646fdc170e74f1f03b}{DMA\_SxCR\_PINC}},\ IncrementMode);}
\DoxyCodeLine{00710\ \}}
\DoxyCodeLine{00711\ }
\DoxyCodeLine{00729\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetPeriphIncMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00730\ \{}
\DoxyCodeLine{00731\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00732\ }
\DoxyCodeLine{00733\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga29c5d5c559dd14646fdc170e74f1f03b}{DMA\_SxCR\_PINC}}));}
\DoxyCodeLine{00734\ \}}
\DoxyCodeLine{00735\ }
\DoxyCodeLine{00754\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMemoryIncMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ IncrementMode)}
\DoxyCodeLine{00755\ \{}
\DoxyCodeLine{00756\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00757\ }
\DoxyCodeLine{00758\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga771a295832a584a3777ede523a691719}{DMA\_SxCR\_MINC}},\ IncrementMode);}
\DoxyCodeLine{00759\ \}}
\DoxyCodeLine{00760\ }
\DoxyCodeLine{00778\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMemoryIncMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00779\ \{}
\DoxyCodeLine{00780\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00781\ }
\DoxyCodeLine{00782\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga771a295832a584a3777ede523a691719}{DMA\_SxCR\_MINC}}));}
\DoxyCodeLine{00783\ \}}
\DoxyCodeLine{00784\ }
\DoxyCodeLine{00804\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetPeriphSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ \ Size)}
\DoxyCodeLine{00805\ \{}
\DoxyCodeLine{00806\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00807\ }
\DoxyCodeLine{00808\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ DMA\_SxCR\_PSIZE,\ Size);}
\DoxyCodeLine{00809\ \}}
\DoxyCodeLine{00810\ }
\DoxyCodeLine{00829\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetPeriphSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00830\ \{}
\DoxyCodeLine{00831\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00832\ }
\DoxyCodeLine{00833\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ DMA\_SxCR\_PSIZE));}
\DoxyCodeLine{00834\ \}}
\DoxyCodeLine{00835\ }
\DoxyCodeLine{00855\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMemorySize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ \ Size)}
\DoxyCodeLine{00856\ \{}
\DoxyCodeLine{00857\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00858\ }
\DoxyCodeLine{00859\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae9a98cb706a722d726d8ec6e9fe4a773}{DMA\_SxCR\_MSIZE}},\ Size);}
\DoxyCodeLine{00860\ \}}
\DoxyCodeLine{00861\ }
\DoxyCodeLine{00880\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMemorySize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00881\ \{}
\DoxyCodeLine{00882\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00883\ }
\DoxyCodeLine{00884\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae9a98cb706a722d726d8ec6e9fe4a773}{DMA\_SxCR\_MSIZE}}));}
\DoxyCodeLine{00885\ \}}
\DoxyCodeLine{00886\ }
\DoxyCodeLine{00905\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetIncOffsetSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ OffsetSize)}
\DoxyCodeLine{00906\ \{}
\DoxyCodeLine{00907\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00908\ }
\DoxyCodeLine{00909\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeb929908d2e7fdef2136c20c93377c70}{DMA\_SxCR\_PINCOS}},\ OffsetSize);}
\DoxyCodeLine{00910\ \}}
\DoxyCodeLine{00911\ }
\DoxyCodeLine{00929\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetIncOffsetSize(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00930\ \{}
\DoxyCodeLine{00931\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00932\ }
\DoxyCodeLine{00933\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeb929908d2e7fdef2136c20c93377c70}{DMA\_SxCR\_PINCOS}}));}
\DoxyCodeLine{00934\ \}}
\DoxyCodeLine{00935\ }
\DoxyCodeLine{00956\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetStreamPriorityLevel(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ \ Priority)}
\DoxyCodeLine{00957\ \{}
\DoxyCodeLine{00958\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00959\ }
\DoxyCodeLine{00960\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga14c115d71a4e3b3c4da360108288154c}{DMA\_SxCR\_PL}},\ Priority);}
\DoxyCodeLine{00961\ \}}
\DoxyCodeLine{00962\ }
\DoxyCodeLine{00982\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetStreamPriorityLevel(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{00983\ \{}
\DoxyCodeLine{00984\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{00985\ }
\DoxyCodeLine{00986\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga14c115d71a4e3b3c4da360108288154c}{DMA\_SxCR\_PL}}));}
\DoxyCodeLine{00987\ \}}
\DoxyCodeLine{00988\ }
\DoxyCodeLine{01004\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableBufferableTransfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01005\ \{}
\DoxyCodeLine{01006\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01007\ }
\DoxyCodeLine{01008\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40a8216c2ca395553c72b00d087087c6}{DMA\_SxCR\_TRBUFF}});}
\DoxyCodeLine{01009\ \}}
\DoxyCodeLine{01010\ }
\DoxyCodeLine{01026\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableBufferableTransfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01027\ \{}
\DoxyCodeLine{01028\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01029\ }
\DoxyCodeLine{01030\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga40a8216c2ca395553c72b00d087087c6}{DMA\_SxCR\_TRBUFF}});}
\DoxyCodeLine{01031\ \}}
\DoxyCodeLine{01032\ }
\DoxyCodeLine{01051\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetDataLength(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ NbData)}
\DoxyCodeLine{01052\ \{}
\DoxyCodeLine{01053\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01054\ }
\DoxyCodeLine{01055\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>NDTR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga62e0e1a1121885de705e618855ba83b0}{DMA\_SxNDT}},\ NbData);}
\DoxyCodeLine{01056\ \}}
\DoxyCodeLine{01057\ }
\DoxyCodeLine{01075\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetDataLength(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01076\ \{}
\DoxyCodeLine{01077\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01078\ }
\DoxyCodeLine{01079\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>NDTR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga62e0e1a1121885de705e618855ba83b0}{DMA\_SxNDT}}));}
\DoxyCodeLine{01080\ \}}
\DoxyCodeLine{01238\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetPeriphRequest(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Request)}
\DoxyCodeLine{01239\ \{}
\DoxyCodeLine{01240\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a_m_u_x___channel___type_def}{DMAMUX\_Channel\_TypeDef}}\ *)(uint32\_t)((uint32\_t)DMAMUX1\_Channel0\ +\ (DMAMUX\_CCR\_SIZE\ *\ (Stream))\ +\ (uint32\_t)(DMAMUX\_CCR\_SIZE\ *\ LL\_DMA\_INSTANCE\_TO\_DMAMUX\_CHANNEL(DMAx))))-\/>CCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga429e04913f0ea2ec973e5e82c0264766}{DMAMUX\_CxCR\_DMAREQ\_ID}},\ Request);}
\DoxyCodeLine{01241\ \}}
\DoxyCodeLine{01242\ }
\DoxyCodeLine{01399\ \_\_STATIC\_INLINE\ \ uint32\_t\ LL\_DMA\_GetPeriphRequest(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01400\ \{}
\DoxyCodeLine{01401\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a_m_u_x___channel___type_def}{DMAMUX\_Channel\_TypeDef}}\ *)((uint32\_t)((uint32\_t)DMAMUX1\_Channel0\ +\ (DMAMUX\_CCR\_SIZE\ *\ (Stream))\ +\ (uint32\_t)(DMAMUX\_CCR\_SIZE\ *\ LL\_DMA\_INSTANCE\_TO\_DMAMUX\_CHANNEL(DMAx)))))-\/>CCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga429e04913f0ea2ec973e5e82c0264766}{DMAMUX\_CxCR\_DMAREQ\_ID}}));}
\DoxyCodeLine{01402\ \}}
\DoxyCodeLine{01403\ }
\DoxyCodeLine{01424\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMemoryBurstxfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Mburst)}
\DoxyCodeLine{01425\ \{}
\DoxyCodeLine{01426\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01427\ }
\DoxyCodeLine{01428\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c1174bff38faf5d87b71521bce8f84f}{DMA\_SxCR\_MBURST}},\ Mburst);}
\DoxyCodeLine{01429\ \}}
\DoxyCodeLine{01430\ }
\DoxyCodeLine{01450\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMemoryBurstxfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01451\ \{}
\DoxyCodeLine{01452\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01453\ }
\DoxyCodeLine{01454\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5c1174bff38faf5d87b71521bce8f84f}{DMA\_SxCR\_MBURST}}));}
\DoxyCodeLine{01455\ \}}
\DoxyCodeLine{01456\ }
\DoxyCodeLine{01477\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetPeriphBurstxfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Pburst)}
\DoxyCodeLine{01478\ \{}
\DoxyCodeLine{01479\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01480\ }
\DoxyCodeLine{01481\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga502380abb155eb3b37a2ca9359e2da2e}{DMA\_SxCR\_PBURST}},\ Pburst);}
\DoxyCodeLine{01482\ \}}
\DoxyCodeLine{01483\ }
\DoxyCodeLine{01503\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetPeriphBurstxfer(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01504\ \{}
\DoxyCodeLine{01505\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01506\ }
\DoxyCodeLine{01507\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga502380abb155eb3b37a2ca9359e2da2e}{DMA\_SxCR\_PBURST}}));}
\DoxyCodeLine{01508\ \}}
\DoxyCodeLine{01509\ }
\DoxyCodeLine{01528\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetCurrentTargetMem(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ CurrentMemory)}
\DoxyCodeLine{01529\ \{}
\DoxyCodeLine{01530\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01531\ }
\DoxyCodeLine{01532\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd36c677ee53f56dc408cd549e64cf7d}{DMA\_SxCR\_CT}},\ CurrentMemory);}
\DoxyCodeLine{01533\ \}}
\DoxyCodeLine{01534\ }
\DoxyCodeLine{01552\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetCurrentTargetMem(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01553\ \{}
\DoxyCodeLine{01554\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01555\ }
\DoxyCodeLine{01556\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadd36c677ee53f56dc408cd549e64cf7d}{DMA\_SxCR\_CT}}));}
\DoxyCodeLine{01557\ \}}
\DoxyCodeLine{01558\ }
\DoxyCodeLine{01574\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableDoubleBufferMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01575\ \{}
\DoxyCodeLine{01576\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01577\ }
\DoxyCodeLine{01578\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\_SxCR\_DBM}});}
\DoxyCodeLine{01579\ \}}
\DoxyCodeLine{01580\ }
\DoxyCodeLine{01596\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableDoubleBufferMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01597\ \{}
\DoxyCodeLine{01598\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01599\ }
\DoxyCodeLine{01600\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\_SxCR\_DBM}});}
\DoxyCodeLine{01601\ \}}
\DoxyCodeLine{01602\ }
\DoxyCodeLine{01618\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledDoubleBufferMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01619\ \{}
\DoxyCodeLine{01620\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01621\ }
\DoxyCodeLine{01622\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\_SxCR\_DBM}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga53a1cde736b2afc5a394a67849f0c497}{DMA\_SxCR\_DBM}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{01623\ \}}
\DoxyCodeLine{01624\ }
\DoxyCodeLine{01646\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetFIFOStatus(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01647\ \{}
\DoxyCodeLine{01648\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01649\ }
\DoxyCodeLine{01650\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga56094479dc9b173b00ccfb199d8a2853}{DMA\_SxFCR\_FS}}));}
\DoxyCodeLine{01651\ \}}
\DoxyCodeLine{01652\ }
\DoxyCodeLine{01668\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableFifoMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01669\ \{}
\DoxyCodeLine{01670\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01671\ }
\DoxyCodeLine{01672\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga89406bb954742665691c0ac2f8d95ec9}{DMA\_SxFCR\_DMDIS}});}
\DoxyCodeLine{01673\ \}}
\DoxyCodeLine{01674\ }
\DoxyCodeLine{01690\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableFifoMode(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01691\ \{}
\DoxyCodeLine{01692\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01693\ }
\DoxyCodeLine{01694\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga89406bb954742665691c0ac2f8d95ec9}{DMA\_SxFCR\_DMDIS}});}
\DoxyCodeLine{01695\ \}}
\DoxyCodeLine{01696\ }
\DoxyCodeLine{01717\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetFIFOThreshold(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Threshold)}
\DoxyCodeLine{01718\ \{}
\DoxyCodeLine{01719\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01720\ }
\DoxyCodeLine{01721\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44c16978164026a81f5b07280e800e7f}{DMA\_SxFCR\_FTH}},\ Threshold);}
\DoxyCodeLine{01722\ \}}
\DoxyCodeLine{01723\ }
\DoxyCodeLine{01743\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetFIFOThreshold(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01744\ \{}
\DoxyCodeLine{01745\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01746\ }
\DoxyCodeLine{01747\ \ \ \textcolor{keywordflow}{return}\ (READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44c16978164026a81f5b07280e800e7f}{DMA\_SxFCR\_FTH}}));}
\DoxyCodeLine{01748\ \}}
\DoxyCodeLine{01749\ }
\DoxyCodeLine{01774\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ConfigFifo(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ FifoMode,\ uint32\_t\ FifoThreshold)}
\DoxyCodeLine{01775\ \{}
\DoxyCodeLine{01776\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01777\ }
\DoxyCodeLine{01778\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44c16978164026a81f5b07280e800e7f}{DMA\_SxFCR\_FTH}}\ |\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga89406bb954742665691c0ac2f8d95ec9}{DMA\_SxFCR\_DMDIS}},\ FifoMode\ |\ FifoThreshold);}
\DoxyCodeLine{01779\ \}}
\DoxyCodeLine{01780\ }
\DoxyCodeLine{01804\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ConfigAddresses(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ SrcAddress,\ uint32\_t\ DstAddress,\ uint32\_t\ Direction)}
\DoxyCodeLine{01805\ \{}
\DoxyCodeLine{01806\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01807\ }
\DoxyCodeLine{01808\ \ \ \textcolor{comment}{/*\ Direction\ Memory\ to\ Periph\ */}}
\DoxyCodeLine{01809\ \ \ \textcolor{keywordflow}{if}\ (Direction\ ==\ LL\_DMA\_DIRECTION\_MEMORY\_TO\_PERIPH)}
\DoxyCodeLine{01810\ \ \ \{}
\DoxyCodeLine{01811\ \ \ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR,\ SrcAddress);}
\DoxyCodeLine{01812\ \ \ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR,\ DstAddress);}
\DoxyCodeLine{01813\ \ \ \}}
\DoxyCodeLine{01814\ \ \ \textcolor{comment}{/*\ Direction\ Periph\ to\ Memory\ and\ Memory\ to\ Memory\ */}}
\DoxyCodeLine{01815\ \ \ \textcolor{keywordflow}{else}}
\DoxyCodeLine{01816\ \ \ \{}
\DoxyCodeLine{01817\ \ \ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR,\ SrcAddress);}
\DoxyCodeLine{01818\ \ \ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR,\ DstAddress);}
\DoxyCodeLine{01819\ \ \ \}}
\DoxyCodeLine{01820\ \}}
\DoxyCodeLine{01821\ }
\DoxyCodeLine{01840\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMemoryAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ MemoryAddress)}
\DoxyCodeLine{01841\ \{}
\DoxyCodeLine{01842\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01843\ }
\DoxyCodeLine{01844\ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR,\ MemoryAddress);}
\DoxyCodeLine{01845\ \}}
\DoxyCodeLine{01846\ }
\DoxyCodeLine{01865\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetPeriphAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ PeriphAddress)}
\DoxyCodeLine{01866\ \{}
\DoxyCodeLine{01867\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01868\ }
\DoxyCodeLine{01869\ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR,\ PeriphAddress);}
\DoxyCodeLine{01870\ \}}
\DoxyCodeLine{01871\ }
\DoxyCodeLine{01888\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMemoryAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01889\ \{}
\DoxyCodeLine{01890\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01891\ }
\DoxyCodeLine{01892\ \ \ \textcolor{keywordflow}{return}\ (READ\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR));}
\DoxyCodeLine{01893\ \}}
\DoxyCodeLine{01894\ }
\DoxyCodeLine{01911\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetPeriphAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01912\ \{}
\DoxyCodeLine{01913\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01914\ }
\DoxyCodeLine{01915\ \ \ \textcolor{keywordflow}{return}\ (READ\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR));}
\DoxyCodeLine{01916\ \}}
\DoxyCodeLine{01917\ }
\DoxyCodeLine{01936\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetM2MSrcAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ MemoryAddress)}
\DoxyCodeLine{01937\ \{}
\DoxyCodeLine{01938\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01939\ }
\DoxyCodeLine{01940\ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR,\ MemoryAddress);}
\DoxyCodeLine{01941\ \}}
\DoxyCodeLine{01942\ }
\DoxyCodeLine{01961\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetM2MDstAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ MemoryAddress)}
\DoxyCodeLine{01962\ \{}
\DoxyCodeLine{01963\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01964\ }
\DoxyCodeLine{01965\ \ \ WRITE\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR,\ MemoryAddress);}
\DoxyCodeLine{01966\ \}}
\DoxyCodeLine{01967\ }
\DoxyCodeLine{01984\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetM2MSrcAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{01985\ \{}
\DoxyCodeLine{01986\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{01987\ }
\DoxyCodeLine{01988\ \ \ \textcolor{keywordflow}{return}\ (READ\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>PAR));}
\DoxyCodeLine{01989\ \}}
\DoxyCodeLine{01990\ }
\DoxyCodeLine{02007\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetM2MDstAddress(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{02008\ \{}
\DoxyCodeLine{02009\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{02010\ }
\DoxyCodeLine{02011\ \ \ \textcolor{keywordflow}{return}\ (READ\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M0AR));}
\DoxyCodeLine{02012\ \}}
\DoxyCodeLine{02013\ }
\DoxyCodeLine{02030\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_SetMemory1Address(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ uint32\_t\ Address)}
\DoxyCodeLine{02031\ \{}
\DoxyCodeLine{02032\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{02033\ }
\DoxyCodeLine{02034\ \ \ MODIFY\_REG(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M1AR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae057bfb6e5d7b553b668a050fcdb152d}{DMA\_SxM1AR\_M1A}},\ Address);}
\DoxyCodeLine{02035\ \}}
\DoxyCodeLine{02036\ }
\DoxyCodeLine{02052\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_GetMemory1Address(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{02053\ \{}
\DoxyCodeLine{02054\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{02055\ }
\DoxyCodeLine{02056\ \ \ \textcolor{keywordflow}{return}\ (((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>M1AR);}
\DoxyCodeLine{02057\ \}}
\DoxyCodeLine{02058\ }
\DoxyCodeLine{02062\ }
\DoxyCodeLine{02066\ }
\DoxyCodeLine{02073\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT0(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02074\ \{}
\DoxyCodeLine{02075\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6181727d13abbc46283ff22ce359e3b9}{DMA\_LISR\_HTIF0}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6181727d13abbc46283ff22ce359e3b9}{DMA\_LISR\_HTIF0}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02076\ \}}
\DoxyCodeLine{02077\ }
\DoxyCodeLine{02084\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02085\ \{}
\DoxyCodeLine{02086\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga04304a9f8891e325247c0aaa4c9fac72}{DMA\_LISR\_HTIF1}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga04304a9f8891e325247c0aaa4c9fac72}{DMA\_LISR\_HTIF1}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02087\ \}}
\DoxyCodeLine{02088\ }
\DoxyCodeLine{02095\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02096\ \{}
\DoxyCodeLine{02097\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ca25185d14a1f0c208ec8ceadc787a6}{DMA\_LISR\_HTIF2}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ca25185d14a1f0c208ec8ceadc787a6}{DMA\_LISR\_HTIF2}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02098\ \}}
\DoxyCodeLine{02099\ }
\DoxyCodeLine{02106\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02107\ \{}
\DoxyCodeLine{02108\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa10c891ee2ec333b7f87eea5886d574f}{DMA\_LISR\_HTIF3}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa10c891ee2ec333b7f87eea5886d574f}{DMA\_LISR\_HTIF3}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02109\ \}}
\DoxyCodeLine{02110\ }
\DoxyCodeLine{02117\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02118\ \{}
\DoxyCodeLine{02119\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadba8d24329c676d70560eda0b8c1e5b0}{DMA\_HISR\_HTIF4}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadba8d24329c676d70560eda0b8c1e5b0}{DMA\_HISR\_HTIF4}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02120\ \}}
\DoxyCodeLine{02121\ }
\DoxyCodeLine{02128\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02129\ \{}
\DoxyCodeLine{02130\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8617bf8160d1027879ffd354e04908d9}{DMA\_HISR\_HTIF5}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga8617bf8160d1027879ffd354e04908d9}{DMA\_HISR\_HTIF5}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02131\ \}}
\DoxyCodeLine{02132\ }
\DoxyCodeLine{02139\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02140\ \{}
\DoxyCodeLine{02141\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0d39c14138e9ff216c203b288137144b}{DMA\_HISR\_HTIF6}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0d39c14138e9ff216c203b288137144b}{DMA\_HISR\_HTIF6}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02142\ \}}
\DoxyCodeLine{02143\ }
\DoxyCodeLine{02150\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_HT7(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02151\ \{}
\DoxyCodeLine{02152\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf535d1a3209d2e2e0e616e2d7501525d}{DMA\_HISR\_HTIF7}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf535d1a3209d2e2e0e616e2d7501525d}{DMA\_HISR\_HTIF7}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02153\ \}}
\DoxyCodeLine{02154\ }
\DoxyCodeLine{02161\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC0(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02162\ \{}
\DoxyCodeLine{02163\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadbc3f7e52c0688bed4b71fa37666901d}{DMA\_LISR\_TCIF0}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadbc3f7e52c0688bed4b71fa37666901d}{DMA\_LISR\_TCIF0}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02164\ \}}
\DoxyCodeLine{02165\ }
\DoxyCodeLine{02172\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02173\ \{}
\DoxyCodeLine{02174\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae02aec39ded937b3ce816d3df4520d9b}{DMA\_LISR\_TCIF1}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae02aec39ded937b3ce816d3df4520d9b}{DMA\_LISR\_TCIF1}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02175\ \}}
\DoxyCodeLine{02176\ }
\DoxyCodeLine{02183\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02184\ \{}
\DoxyCodeLine{02185\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf21350cce8c4cb5d7c6fcf5edc930cf8}{DMA\_LISR\_TCIF2}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf21350cce8c4cb5d7c6fcf5edc930cf8}{DMA\_LISR\_TCIF2}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02186\ \}}
\DoxyCodeLine{02187\ }
\DoxyCodeLine{02194\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02195\ \{}
\DoxyCodeLine{02196\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44e5bf8adbb2646d325cba8d5dd670d8}{DMA\_LISR\_TCIF3}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44e5bf8adbb2646d325cba8d5dd670d8}{DMA\_LISR\_TCIF3}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02197\ \}}
\DoxyCodeLine{02198\ }
\DoxyCodeLine{02205\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02206\ \{}
\DoxyCodeLine{02207\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafcce25c245499f9e62cb757e1871d973}{DMA\_HISR\_TCIF4}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafcce25c245499f9e62cb757e1871d973}{DMA\_HISR\_TCIF4}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02208\ \}}
\DoxyCodeLine{02209\ }
\DoxyCodeLine{02216\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02217\ \{}
\DoxyCodeLine{02218\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga64f15eaf1dd30450d1d35ee517507321}{DMA\_HISR\_TCIF5}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga64f15eaf1dd30450d1d35ee517507321}{DMA\_HISR\_TCIF5}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02219\ \}}
\DoxyCodeLine{02220\ }
\DoxyCodeLine{02227\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02228\ \{}
\DoxyCodeLine{02229\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad29468aa609150e241d9ae62c477cf45}{DMA\_HISR\_TCIF6}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad29468aa609150e241d9ae62c477cf45}{DMA\_HISR\_TCIF6}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02230\ \}}
\DoxyCodeLine{02231\ }
\DoxyCodeLine{02238\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TC7(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02239\ \{}
\DoxyCodeLine{02240\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad20a0a5e103def436d4e329fc0888482}{DMA\_HISR\_TCIF7}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad20a0a5e103def436d4e329fc0888482}{DMA\_HISR\_TCIF7}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02241\ \}}
\DoxyCodeLine{02242\ }
\DoxyCodeLine{02249\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE0(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02250\ \{}
\DoxyCodeLine{02251\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad43cdafa5acfcd683b7a2ee8976dd8ba}{DMA\_LISR\_TEIF0}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad43cdafa5acfcd683b7a2ee8976dd8ba}{DMA\_LISR\_TEIF0}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02252\ \}}
\DoxyCodeLine{02253\ }
\DoxyCodeLine{02260\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02261\ \{}
\DoxyCodeLine{02262\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0cd826db0b9ea5544d1a93beb90f8972}{DMA\_LISR\_TEIF1}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0cd826db0b9ea5544d1a93beb90f8972}{DMA\_LISR\_TEIF1}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02263\ \}}
\DoxyCodeLine{02264\ }
\DoxyCodeLine{02271\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02272\ \{}
\DoxyCodeLine{02273\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga74d540802cadde42bdd6debae5d8ab89}{DMA\_LISR\_TEIF2}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga74d540802cadde42bdd6debae5d8ab89}{DMA\_LISR\_TEIF2}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02274\ \}}
\DoxyCodeLine{02275\ }
\DoxyCodeLine{02282\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02283\ \{}
\DoxyCodeLine{02284\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5dfaba3a5db7cdcbddf9ee5974b44c2f}{DMA\_LISR\_TEIF3}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5dfaba3a5db7cdcbddf9ee5974b44c2f}{DMA\_LISR\_TEIF3}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02285\ \}}
\DoxyCodeLine{02286\ }
\DoxyCodeLine{02293\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02294\ \{}
\DoxyCodeLine{02295\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9005d4b958193fbd701c879eede467c1}{DMA\_HISR\_TEIF4}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9005d4b958193fbd701c879eede467c1}{DMA\_HISR\_TEIF4}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02296\ \}}
\DoxyCodeLine{02297\ }
\DoxyCodeLine{02304\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
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\DoxyCodeLine{02307\ \}}
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\DoxyCodeLine{02315\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
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\DoxyCodeLine{02318\ \}}
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\DoxyCodeLine{02326\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_TE7(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
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\DoxyCodeLine{02329\ \}}
\DoxyCodeLine{02330\ }
\DoxyCodeLine{02337\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME0(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02338\ \{}
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\DoxyCodeLine{02340\ \}}
\DoxyCodeLine{02341\ }
\DoxyCodeLine{02348\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02349\ \{}
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\DoxyCodeLine{02351\ \}}
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\DoxyCodeLine{02359\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02360\ \{}
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\DoxyCodeLine{02362\ \}}
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\DoxyCodeLine{02370\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02371\ \{}
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\DoxyCodeLine{02373\ \}}
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\DoxyCodeLine{02381\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02382\ \{}
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\DoxyCodeLine{02384\ \}}
\DoxyCodeLine{02385\ }
\DoxyCodeLine{02392\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02393\ \{}
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\DoxyCodeLine{02395\ \}}
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\DoxyCodeLine{02403\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02404\ \{}
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\DoxyCodeLine{02406\ \}}
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\DoxyCodeLine{02414\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_DME7(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02415\ \{}
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\DoxyCodeLine{02417\ \}}
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\DoxyCodeLine{02425\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE0(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02426\ \{}
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\DoxyCodeLine{02428\ \}}
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\DoxyCodeLine{02436\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE1(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02437\ \{}
\DoxyCodeLine{02438\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafbc4fecde60c09e12f10113a156bb922}{DMA\_LISR\_FEIF1}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafbc4fecde60c09e12f10113a156bb922}{DMA\_LISR\_FEIF1}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02439\ \}}
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\DoxyCodeLine{02447\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE2(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02448\ \{}
\DoxyCodeLine{02449\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_aacb4a0977d281bc809cb5974e178bc2b}{LISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga99c42b194213872753460ef9b7745213}{DMA\_LISR\_FEIF2}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga99c42b194213872753460ef9b7745213}{DMA\_LISR\_FEIF2}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02450\ \}}
\DoxyCodeLine{02451\ }
\DoxyCodeLine{02458\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE3(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02459\ \{}
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\DoxyCodeLine{02461\ \}}
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\DoxyCodeLine{02469\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE4(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02470\ \{}
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\DoxyCodeLine{02472\ \}}
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\DoxyCodeLine{02480\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE5(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02481\ \{}
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\DoxyCodeLine{02483\ \}}
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\DoxyCodeLine{02491\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE6(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02492\ \{}
\DoxyCodeLine{02493\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafb297f94bde8d1aea580683d466ca8ca}{DMA\_HISR\_FEIF6}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gafb297f94bde8d1aea580683d466ca8ca}{DMA\_HISR\_FEIF6}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02494\ \}}
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\DoxyCodeLine{02502\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsActiveFlag\_FE7(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02503\ \{}
\DoxyCodeLine{02504\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a01a90a5fcd6459e10b81c0ab737dd2e3}{HISR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadea53385fca360f16c4474db1cf18bc1}{DMA\_HISR\_FEIF7}})\ ==\ (\mbox{\hyperlink{group___peripheral___registers___bits___definition_gadea53385fca360f16c4474db1cf18bc1}{DMA\_HISR\_FEIF7}}))\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{02505\ \}}
\DoxyCodeLine{02506\ }
\DoxyCodeLine{02513\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT0(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02514\ \{}
\DoxyCodeLine{02515\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga44f83ba08feb98240a553403d977b8d1}{DMA\_LIFCR\_CHTIF0}});}
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\DoxyCodeLine{02524\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT1(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02525\ \{}
\DoxyCodeLine{02526\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad2f38b0c141a9afb3943276dacdcb969}{DMA\_LIFCR\_CHTIF1}});}
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\DoxyCodeLine{02535\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT2(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02536\ \{}
\DoxyCodeLine{02537\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae19254e8ad726a73c6edc01bc7cf2cfa}{DMA\_LIFCR\_CHTIF2}});}
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\DoxyCodeLine{02546\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT3(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02547\ \{}
\DoxyCodeLine{02548\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0ed3ab4e5d7975f985eb25dc65f99be3}{DMA\_LIFCR\_CHTIF3}});}
\DoxyCodeLine{02549\ \}}
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\DoxyCodeLine{02557\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT4(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02558\ \{}
\DoxyCodeLine{02559\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8f0afa9a6526f7f4413766417a56be8}{DMA\_HIFCR\_CHTIF4}});}
\DoxyCodeLine{02560\ \}}
\DoxyCodeLine{02561\ }
\DoxyCodeLine{02568\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT5(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02569\ \{}
\DoxyCodeLine{02570\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga2cef7eeccd11737c1ebf5735284046cc}{DMA\_HIFCR\_CHTIF5}});}
\DoxyCodeLine{02571\ \}}
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\DoxyCodeLine{02579\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT6(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02580\ \{}
\DoxyCodeLine{02581\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaed7cbbbc0602d00e101e3f57aa3b696a}{DMA\_HIFCR\_CHTIF6}});}
\DoxyCodeLine{02582\ \}}
\DoxyCodeLine{02583\ }
\DoxyCodeLine{02590\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_HT7(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02591\ \{}
\DoxyCodeLine{02592\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga95e9989cbd70b18d833bb4cfcb8afce9}{DMA\_HIFCR\_CHTIF7}});}
\DoxyCodeLine{02593\ \}}
\DoxyCodeLine{02594\ }
\DoxyCodeLine{02601\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC0(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02602\ \{}
\DoxyCodeLine{02603\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gab7a0b2cc41c63504195714614e59dc8e}{DMA\_LIFCR\_CTCIF0}});}
\DoxyCodeLine{02604\ \}}
\DoxyCodeLine{02605\ }
\DoxyCodeLine{02612\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC1(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02613\ \{}
\DoxyCodeLine{02614\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7494c54901b8f5bcb4894d20b8cfafed}{DMA\_LIFCR\_CTCIF1}});}
\DoxyCodeLine{02615\ \}}
\DoxyCodeLine{02616\ }
\DoxyCodeLine{02623\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC2(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02624\ \{}
\DoxyCodeLine{02625\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga52d6df2b5ab2b43da273a702fe139b59}{DMA\_LIFCR\_CTCIF2}});}
\DoxyCodeLine{02626\ \}}
\DoxyCodeLine{02627\ }
\DoxyCodeLine{02634\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC3(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02635\ \{}
\DoxyCodeLine{02636\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5210736d34dc24eb9507975921233137}{DMA\_LIFCR\_CTCIF3}});}
\DoxyCodeLine{02637\ \}}
\DoxyCodeLine{02638\ }
\DoxyCodeLine{02645\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC4(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02646\ \{}
\DoxyCodeLine{02647\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga42e529507a40f0dc4c16da7cc6d659db}{DMA\_HIFCR\_CTCIF4}});}
\DoxyCodeLine{02648\ \}}
\DoxyCodeLine{02649\ }
\DoxyCodeLine{02656\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC5(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02657\ \{}
\DoxyCodeLine{02658\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa55d19705147a6ee16effe9ec1012a72}{DMA\_HIFCR\_CTCIF5}});}
\DoxyCodeLine{02659\ \}}
\DoxyCodeLine{02660\ }
\DoxyCodeLine{02667\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC6(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02668\ \{}
\DoxyCodeLine{02669\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacd88be16962491e41e586f5109014bc6}{DMA\_HIFCR\_CTCIF6}});}
\DoxyCodeLine{02670\ \}}
\DoxyCodeLine{02671\ }
\DoxyCodeLine{02678\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TC7(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02679\ \{}
\DoxyCodeLine{02680\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf8056629f4948fb236b4339e213cc69}{DMA\_HIFCR\_CTCIF7}});}
\DoxyCodeLine{02681\ \}}
\DoxyCodeLine{02682\ }
\DoxyCodeLine{02689\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE0(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02690\ \{}
\DoxyCodeLine{02691\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga5824a64683ce2039260c952d989bf420}{DMA\_LIFCR\_CTEIF0}});}
\DoxyCodeLine{02692\ \}}
\DoxyCodeLine{02693\ }
\DoxyCodeLine{02700\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE1(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02701\ \{}
\DoxyCodeLine{02702\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf6d8adf52567aee2969492db65d448d4}{DMA\_LIFCR\_CTEIF1}});}
\DoxyCodeLine{02703\ \}}
\DoxyCodeLine{02704\ }
\DoxyCodeLine{02711\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE2(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02712\ \{}
\DoxyCodeLine{02713\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa9d761752657a3d268da5434a04c6c6a}{DMA\_LIFCR\_CTEIF2}});}
\DoxyCodeLine{02714\ \}}
\DoxyCodeLine{02715\ }
\DoxyCodeLine{02722\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE3(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02723\ \{}
\DoxyCodeLine{02724\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0a51c601387d1ae49333d5ace8ae86ee}{DMA\_LIFCR\_CTEIF3}});}
\DoxyCodeLine{02725\ \}}
\DoxyCodeLine{02726\ }
\DoxyCodeLine{02733\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE4(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02734\ \{}
\DoxyCodeLine{02735\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9e05ff4fc6bace9cc6c0f0d4ec7b3314}{DMA\_HIFCR\_CTEIF4}});}
\DoxyCodeLine{02736\ \}}
\DoxyCodeLine{02737\ }
\DoxyCodeLine{02744\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE5(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02745\ \{}
\DoxyCodeLine{02746\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga33394fe20a3567c8baaeb15ad9aab586}{DMA\_HIFCR\_CTEIF5}});}
\DoxyCodeLine{02747\ \}}
\DoxyCodeLine{02748\ }
\DoxyCodeLine{02755\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE6(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02756\ \{}
\DoxyCodeLine{02757\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga69e01e2f6a5cd1c800321e4121f8e788}{DMA\_HIFCR\_CTEIF6}});}
\DoxyCodeLine{02758\ \}}
\DoxyCodeLine{02759\ }
\DoxyCodeLine{02766\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_TE7(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02767\ \{}
\DoxyCodeLine{02768\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga84ab215e0b217547745beefb65dfefdf}{DMA\_HIFCR\_CTEIF7}});}
\DoxyCodeLine{02769\ \}}
\DoxyCodeLine{02770\ }
\DoxyCodeLine{02777\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME0(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02778\ \{}
\DoxyCodeLine{02779\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gafe80a122bf0537e8c95877ccf2b7b6d9}{DMA\_LIFCR\_CDMEIF0}});}
\DoxyCodeLine{02780\ \}}
\DoxyCodeLine{02781\ }
\DoxyCodeLine{02788\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME1(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02789\ \{}
\DoxyCodeLine{02790\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9a5aea54a390886f7de82e87e6dfc936}{DMA\_LIFCR\_CDMEIF1}});}
\DoxyCodeLine{02791\ \}}
\DoxyCodeLine{02792\ }
\DoxyCodeLine{02799\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME2(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02800\ \{}
\DoxyCodeLine{02801\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7680fc5f5e6c0032044f1d8ab7766de8}{DMA\_LIFCR\_CDMEIF2}});}
\DoxyCodeLine{02802\ \}}
\DoxyCodeLine{02803\ }
\DoxyCodeLine{02810\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME3(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02811\ \{}
\DoxyCodeLine{02812\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gabea10cdf2d3b0773b4e6b7fc9422f361}{DMA\_LIFCR\_CDMEIF3}});}
\DoxyCodeLine{02813\ \}}
\DoxyCodeLine{02814\ }
\DoxyCodeLine{02821\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME4(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02822\ \{}
\DoxyCodeLine{02823\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga0d70d58a4423ac8973c30ddbc7404b44}{DMA\_HIFCR\_CDMEIF4}});}
\DoxyCodeLine{02824\ \}}
\DoxyCodeLine{02825\ }
\DoxyCodeLine{02832\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME5(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02833\ \{}
\DoxyCodeLine{02834\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga15b404d9e1601cf3627cbf0163b50221}{DMA\_HIFCR\_CDMEIF5}});}
\DoxyCodeLine{02835\ \}}
\DoxyCodeLine{02836\ }
\DoxyCodeLine{02843\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME6(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02844\ \{}
\DoxyCodeLine{02845\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga7f73fa93a4e01fbf279e920eca139807}{DMA\_HIFCR\_CDMEIF6}});}
\DoxyCodeLine{02846\ \}}
\DoxyCodeLine{02847\ }
\DoxyCodeLine{02854\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_DME7(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02855\ \{}
\DoxyCodeLine{02856\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad70bf852fd8c24d79fcc104c950a589f}{DMA\_HIFCR\_CDMEIF7}});}
\DoxyCodeLine{02857\ \}}
\DoxyCodeLine{02858\ }
\DoxyCodeLine{02865\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE0(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02866\ \{}
\DoxyCodeLine{02867\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gadf6b8892189f3779f7fecf529ed87c74}{DMA\_LIFCR\_CFEIF0}});}
\DoxyCodeLine{02868\ \}}
\DoxyCodeLine{02869\ }
\DoxyCodeLine{02876\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE1(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02877\ \{}
\DoxyCodeLine{02878\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga96cea0049553ab806bbc956f52528c37}{DMA\_LIFCR\_CFEIF1}});}
\DoxyCodeLine{02879\ \}}
\DoxyCodeLine{02880\ }
\DoxyCodeLine{02887\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE2(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02888\ \{}
\DoxyCodeLine{02889\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae0f58173c721a4cee3f3885b352fa2a3}{DMA\_LIFCR\_CFEIF2}});}
\DoxyCodeLine{02890\ \}}
\DoxyCodeLine{02891\ }
\DoxyCodeLine{02898\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE3(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02899\ \{}
\DoxyCodeLine{02900\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a11adb689c874d38b49fa44990323b653}{LIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gad9432964145dc55af9186aea425e9963}{DMA\_LIFCR\_CFEIF3}});}
\DoxyCodeLine{02901\ \}}
\DoxyCodeLine{02902\ }
\DoxyCodeLine{02909\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE4(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02910\ \{}
\DoxyCodeLine{02911\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga1e5ea118900178d4fa2d19656c1b48ff}{DMA\_HIFCR\_CFEIF4}});}
\DoxyCodeLine{02912\ \}}
\DoxyCodeLine{02913\ }
\DoxyCodeLine{02920\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE5(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02921\ \{}
\DoxyCodeLine{02922\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga9a4e90af967fa0a76c842384264e0e52}{DMA\_HIFCR\_CFEIF5}});}
\DoxyCodeLine{02923\ \}}
\DoxyCodeLine{02924\ }
\DoxyCodeLine{02931\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE6(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02932\ \{}
\DoxyCodeLine{02933\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga39a0a7f42498f71dedae8140483b7ced}{DMA\_HIFCR\_CFEIF6}});}
\DoxyCodeLine{02934\ \}}
\DoxyCodeLine{02935\ }
\DoxyCodeLine{02942\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_ClearFlag\_FE7(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx)}
\DoxyCodeLine{02943\ \{}
\DoxyCodeLine{02944\ \ \ WRITE\_REG(DMAx-\/>\mbox{\hyperlink{struct_d_m_a___type_def_a1e4f50b935bab2520788ae936f2e55c1}{HIFCR}},\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga50332abe2e7b5a4f9cffd65d9a29382a}{DMA\_HIFCR\_CFEIF7}});}
\DoxyCodeLine{02945\ \}}
\DoxyCodeLine{02946\ }
\DoxyCodeLine{02950\ }
\DoxyCodeLine{02954\ }
\DoxyCodeLine{02970\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableIT\_HT(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{02971\ \{}
\DoxyCodeLine{02972\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{02973\ }
\DoxyCodeLine{02974\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13a7fe097608bc5031d42ba69effed20}{DMA\_SxCR\_HTIE}});}
\DoxyCodeLine{02975\ \}}
\DoxyCodeLine{02976\ }
\DoxyCodeLine{02992\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableIT\_TE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{02993\ \{}
\DoxyCodeLine{02994\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{02995\ }
\DoxyCodeLine{02996\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeee99c36ba3ea56cdb4f73a0b01fb602}{DMA\_SxCR\_TEIE}});}
\DoxyCodeLine{02997\ \}}
\DoxyCodeLine{02998\ }
\DoxyCodeLine{03014\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableIT\_TC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03015\ \{}
\DoxyCodeLine{03016\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03017\ }
\DoxyCodeLine{03018\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ae47cc2cd2e985d29cb6b0bb65da1d7}{DMA\_SxCR\_TCIE}});}
\DoxyCodeLine{03019\ \}}
\DoxyCodeLine{03020\ }
\DoxyCodeLine{03036\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableIT\_DME(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03037\ \{}
\DoxyCodeLine{03038\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03039\ }
\DoxyCodeLine{03040\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacaecc56f94a9af756d077cf7df1b6c41}{DMA\_SxCR\_DMEIE}});}
\DoxyCodeLine{03041\ \}}
\DoxyCodeLine{03042\ }
\DoxyCodeLine{03058\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_EnableIT\_FE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03059\ \{}
\DoxyCodeLine{03060\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03061\ }
\DoxyCodeLine{03062\ \ \ SET\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaba9ca2264bc381abe0f4183729ab1fb1}{DMA\_SxFCR\_FEIE}});}
\DoxyCodeLine{03063\ \}}
\DoxyCodeLine{03064\ }
\DoxyCodeLine{03080\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableIT\_HT(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03081\ \{}
\DoxyCodeLine{03082\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03083\ }
\DoxyCodeLine{03084\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13a7fe097608bc5031d42ba69effed20}{DMA\_SxCR\_HTIE}});}
\DoxyCodeLine{03085\ \}}
\DoxyCodeLine{03086\ }
\DoxyCodeLine{03102\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableIT\_TE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03103\ \{}
\DoxyCodeLine{03104\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03105\ }
\DoxyCodeLine{03106\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeee99c36ba3ea56cdb4f73a0b01fb602}{DMA\_SxCR\_TEIE}});}
\DoxyCodeLine{03107\ \}}
\DoxyCodeLine{03108\ }
\DoxyCodeLine{03124\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableIT\_TC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03125\ \{}
\DoxyCodeLine{03126\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03127\ }
\DoxyCodeLine{03128\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ae47cc2cd2e985d29cb6b0bb65da1d7}{DMA\_SxCR\_TCIE}});}
\DoxyCodeLine{03129\ \}}
\DoxyCodeLine{03130\ }
\DoxyCodeLine{03146\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableIT\_DME(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03147\ \{}
\DoxyCodeLine{03148\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03149\ }
\DoxyCodeLine{03150\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacaecc56f94a9af756d077cf7df1b6c41}{DMA\_SxCR\_DMEIE}});}
\DoxyCodeLine{03151\ \}}
\DoxyCodeLine{03152\ }
\DoxyCodeLine{03168\ \_\_STATIC\_INLINE\ \textcolor{keywordtype}{void}\ LL\_DMA\_DisableIT\_FE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03169\ \{}
\DoxyCodeLine{03170\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03171\ }
\DoxyCodeLine{03172\ \ \ CLEAR\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaba9ca2264bc381abe0f4183729ab1fb1}{DMA\_SxFCR\_FEIE}});}
\DoxyCodeLine{03173\ \}}
\DoxyCodeLine{03174\ }
\DoxyCodeLine{03190\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledIT\_HT(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03191\ \{}
\DoxyCodeLine{03192\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03193\ }
\DoxyCodeLine{03194\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13a7fe097608bc5031d42ba69effed20}{DMA\_SxCR\_HTIE}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga13a7fe097608bc5031d42ba69effed20}{DMA\_SxCR\_HTIE}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03195\ \}}
\DoxyCodeLine{03196\ }
\DoxyCodeLine{03212\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledIT\_TE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03213\ \{}
\DoxyCodeLine{03214\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03215\ }
\DoxyCodeLine{03216\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeee99c36ba3ea56cdb4f73a0b01fb602}{DMA\_SxCR\_TEIE}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaeee99c36ba3ea56cdb4f73a0b01fb602}{DMA\_SxCR\_TEIE}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03217\ \}}
\DoxyCodeLine{03218\ }
\DoxyCodeLine{03234\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledIT\_TC(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03235\ \{}
\DoxyCodeLine{03236\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03237\ }
\DoxyCodeLine{03238\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ae47cc2cd2e985d29cb6b0bb65da1d7}{DMA\_SxCR\_TCIE}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga6ae47cc2cd2e985d29cb6b0bb65da1d7}{DMA\_SxCR\_TCIE}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03239\ \}}
\DoxyCodeLine{03240\ }
\DoxyCodeLine{03256\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledIT\_DME(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03257\ \{}
\DoxyCodeLine{03258\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03259\ }
\DoxyCodeLine{03260\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>CR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacaecc56f94a9af756d077cf7df1b6c41}{DMA\_SxCR\_DMEIE}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gacaecc56f94a9af756d077cf7df1b6c41}{DMA\_SxCR\_DMEIE}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03261\ \}}
\DoxyCodeLine{03262\ }
\DoxyCodeLine{03278\ \_\_STATIC\_INLINE\ uint32\_t\ LL\_DMA\_IsEnabledIT\_FE(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream)}
\DoxyCodeLine{03279\ \{}
\DoxyCodeLine{03280\ \ \ uint32\_t\ dma\_base\_addr\ =\ (uint32\_t)DMAx;}
\DoxyCodeLine{03281\ }
\DoxyCodeLine{03282\ \ \ \textcolor{keywordflow}{return}\ ((READ\_BIT(((\mbox{\hyperlink{struct_d_m_a___stream___type_def}{DMA\_Stream\_TypeDef}}\ *)(dma\_base\_addr\ +\ LL\_DMA\_STR\_OFFSET\_TAB[Stream]))-\/>FCR,\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaba9ca2264bc381abe0f4183729ab1fb1}{DMA\_SxFCR\_FEIE}})\ ==\ \mbox{\hyperlink{group___peripheral___registers___bits___definition_gaba9ca2264bc381abe0f4183729ab1fb1}{DMA\_SxFCR\_FEIE}})\ ?\ 1UL\ :\ 0UL);}
\DoxyCodeLine{03283\ \}}
\DoxyCodeLine{03284\ }
\DoxyCodeLine{03288\ }
\DoxyCodeLine{03289\ \textcolor{preprocessor}{\#if\ defined(USE\_FULL\_LL\_DRIVER)}\textcolor{preprocessor}{}}
\DoxyCodeLine{03293\ }
\DoxyCodeLine{03294\ uint32\_t\ LL\_DMA\_Init(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream,\ LL\_DMA\_InitTypeDef\ *DMA\_InitStruct);}
\DoxyCodeLine{03295\ uint32\_t\ LL\_DMA\_DeInit(\mbox{\hyperlink{struct_d_m_a___type_def}{DMA\_TypeDef}}\ *DMAx,\ uint32\_t\ Stream);}
\DoxyCodeLine{03296\ \textcolor{keywordtype}{void}\ LL\_DMA\_StructInit(LL\_DMA\_InitTypeDef\ *DMA\_InitStruct);}
\DoxyCodeLine{03297\ }
\DoxyCodeLine{03301\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ USE\_FULL\_LL\_DRIVER\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03302\ }
\DoxyCodeLine{03306\ }
\DoxyCodeLine{03310\ }
\DoxyCodeLine{03311\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ DMA1\ ||\ DMA2\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03312\ }
\DoxyCodeLine{03316\ }
\DoxyCodeLine{03317\ \textcolor{preprocessor}{\#ifdef\ \_\_cplusplus}}
\DoxyCodeLine{03318\ \}}
\DoxyCodeLine{03319\ \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{03320\ }
\DoxyCodeLine{03321\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ \_\_STM32H7xx\_LL\_DMA\_H\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03322\ }

\end{DoxyCode}
